The present invention relates to a system that accommodates agents having different schemes for managing access to a common resource. Typically, the present invention may be applied so as to enable a single system to employ data processors having different techniques for managing access to a common memory. A non-limitative example of such a system is an MPEG codec (coder-decoder implementing the standards defined by the Motion Picture Expert Group).
Various systems exist in which it is necessary for a common resource to be shared between a plurality of agents, only one of the agents at a time being able to access the shared resource. This is the case, for example, in a data processing device in which several processors share a common memory. In the present document, the term xe2x80x9cagentxe2x80x9d is used both to designate a module and a process implemented by a module (it being understood that a given module may implement a plurality of processes).
Different schemes have been adopted to manage the accessing of the shared resource by the individual agents. Some systems adopt a time-slotted accessing scheme in which each agent accesses the shared resource at a predetermined instant, for a predetermined period of time, and the agents access the shared resource, repeatedly, in a predetermined order. Other systems adopt a scheme in which agents make access-requests as and when they require access and, in the event that a plurality of requests are issued at the same time, an arbiter decides which access-request will be successful. The arbiter implements an arbitration scheme that is designed to ensure that each agent will have access to the shared resource for a period of time sufficient for its needs. This is usually considered in terms of the xe2x80x9cbandwidthxe2x80x9d required by each agent.
WO98/12645 describes a method and apparatus for bus arbitration in a system where several devices (central processing unit (CPU), data and instruction caches, image co-processor, etc.) integrated on a microprocessor chip use a shared bus to access a common (synchronous DRAM) memory located off the chip. In this system, there is a weighted allocation of bandwidth to the different agents requiring bus access and the arbiter implements an arbitration scheme that ensures that each device receives the bandwidth allocation it requires.
FIG. 1 illustrates the typical environment of a module designed to use a time-slotted access scheme; in this example the module is a processor, PROC, and the shared resource is a memory, MEM. The module PROC is adapted to access the memory MEM via an interface, INT. Only one module PROC is shown in FIG. 1 but it is to be understood that, in general, several such modules will be integrated onto a single chip IC1. Moreover, although, as illustrated here, the memory interface is provided on-chip, it is to be understood that the present invention is applicable also in the case of re-use of modules designed to be associated with an off-chip memory-interface. The interface INT grants the module PROC access to the memory MEM on the basis of a memory-access scheme according to which predetermined time slots are reserved for the module PROC to transfer data to the memory MEM and/or receive data therefrom.
The interface INT is configurable, that is, the allocation of modules to specific time slots can be changed. A controller CONT applies control data to the interface INT to specify which time slot(s) are to be used for access to memory MEM on behalf of the respective different modules on the chip. The controller CONT also applies control data to the module PROC so as to inform it of the predetermined time slots at which it should fetch data from or write data to the memory MEM (via a buffer internal to the interface INT). The allocation of processing modules to time slots is changed relatively infrequently and, thus, this control data is only sent to the interface and processing modules when a configuration change is required.
In general, each of the processing modules on the chip will repeatedly implement the same processing function, but applied to new data. For example, in the case where the IC1 of FIG. 1 is the core of an MPEG encoder, certain pre-set functions are repeatedly performed on successive macro-blocks making up a frame of an image signal, by a group of processing modules. The controller, CONT, internal to IC1 outputs to the processing modules and the interface synchronization signals (in this example, frame start signals and macro-block start signals) as references for determining when the various predetermined time slots occur. The controller also outputs to the interface address data indicating where in the memory, MEM, data is stored relating to the macro-block or line of pixels to be processed by a given module during a particular time period. This address data will, generally, be defined in terms of a start address, and a number of consecutive address locations to access. In some cases, the address data applicable to a given request to be made by a module depends upon the result of some calculation made by another module (which may be another process of the same physical device). In such a case, the controller receives data regarding the result, from the module performing the calculation and generates address data accordingly.
If the interface INT reads/writes data at a different speed from that used by the module PROC, a buffer, BUF, dedicated to module PROC can be placed between the interface INT and the module PROC, to store the data read from memory, MEM, and intended for this module. In this case, the module PROC is arranged to read/write data from/to the buffer at the predetermined time intervals. In this case, during a read operation, if module PROC does not receive from the buffer an acknowledgement signal indicating that data for it is present in the buffer, operation of this module is stalled until such time a subsequent request is acknowledged.
In the time-slotted memory-access scheme of FIG. 1, the module PROC is designed to receive and/or output data during predetermined time periods of set duration, via requests made to the memory interface (or, in some cases, to a buffer) during said predetermined time periods.
FIG. 2 illustrates a typical system including an arbiter arbitrating between different requests issued from a plurality of agents. Once again, in this example, the agents are processing modules PROCxe2x80x2 sharing a common memory, MEM, and only a single agent on the chip, IC2, is illustrated in FIG. 2. In this case, the interface, INT, incorporates an arbiter, ARB, applying an arbitration scheme to determine which of a plurality of access-requests that are valid at a given instant will be successful. The arbitration scheme may be a round-robin scheme, or it may be based upon priorities (perhaps variable priorities) allocated to the different modules, or it may be any other known arbitration scheme. The successful access request is passed to a memory interface MIF which handles the physical access to the memory MEM and the routing of data between MEM and PROCxe2x80x2.
In this system, it is not known beforehand how much time will intervene between the making of a request by a given module and the granting of access by the arbiter in response to the request. Accordingly, for each module a buffer BUFxe2x80x2 is provided between the module and the interface. This intermediate buffer may be implemented using a single memory (SRAM) having separate portions dedicated to different modules.
In the arbitrated memory-access scheme of FIG. 2, the modules issue access-requests at variable times and of variable duration, and may receive and/or output data at irregular intervals of variable duration.
In some circumstances it may be desirable to employ in a single system modules that have been designed for different resource-accessing schemes. For example, in the context of an MPEG codec, it can arise that encoder and decoder chips (integrated circuits) are designed separately, the decoder chip making use of an arbiter selecting between the access-requests made by the different processes in the decoder whereas the encoder uses a time-slotted access-management scheme to ensure that its component processes have the required access to main memory. Although separate memories could be used for the encoder and decoder chips, this obviously increases costs and complexity of the codec. It would be preferable to use a memory common to both chips and, thus, it is necessary to use a single scheme for managing access to this common memory.
In order to reduce costs, it is preferable to keep the architecture of the different integrated circuits unchanged as far as possible. A priori this counts against the use of a time-slotted memory-access scheme, because data is not readily available regarding the timing and duration of the access-requests made by the modules designed for a request-arbitration scheme.
A request-arbitration memory-access scheme has the advantage that it provides efficient bandwidth partition between the different modules requiring memory access. However, there is a problem with using a request-arbitration scheme for a module PROC designed for a time-slotted scheme because it may be difficult to guarantee that data for PROC will be available at the periodic intervals for which module PROC is programmed.
More particularly, during the intervals at which module PROC xe2x80x9cexpectsxe2x80x9d to read/write data from/to the common memory it requires a high bandwidth access. In some cases, the memory may simply not be designed for such a high bandwidth access (the bus properties are not appropriate). However, even in cases where high-bandwidth access is possible, another module may be accessing the memory already at an instant when a request from module PROC is issued, and this access may be uninterruptible. One solution to this problem would be to change the design of the arbitration scheme so as to give requests from PROC a high priority. However, this solution is not sufficient to remove the risk of data underflow to module PROC during read access.
It is an object of the present invention to enable an agent designed for a time-slotted resource-access scheme to be used in a system employing an arbiter arbitrating between requests of different agents for access to a common (shared) resource.
It is a further object of the present invention to enable costs to be reduced in a system employing: an arbiter arbitrating between requests of different agents for access to a common resource, and at least one agent designed for a time-slotted resource-access scheme.
The invention takes the following aspects into consideration. An anticipatory request-generator is associated with the agent designed for a time-slotted resource-access scheme. Ahead of the time periods when the agent is programmed to receive data from the common resource, the anticipatory request-generator generates access-requests and submits these to the interface managing access to the common resource. The anticipated request will give rise to access to the common resource, according to the arbitration scheme implemented by the interface, before the time period arrives at which the agent requires the data. A buffer is placed between the interface and the agent, for temporarily storing the data received as a result of the anticipated request. During the time periods when the agent is programmed to fetch data it will do so from the buffer. Write-access requests made by the agent at the pre-programmed instants in time will simply be forwarded to the arbiter (optionally, via a buffer).
The agent adapted for a time-slotted resource-accessing scheme is integrated into a system based on request-arbitration by virtue of the presence of the anticipatory request-generator and buffer. In the case where this agent is one of a plurality of agents, all adapted for a time-slotted access scheme, provided on an integrated circuit, minimal changes are required to the IC architecture. It may merely be necessary to modify a pre-existing interface associated with the agents, if this interface was provided on-chip.
The anticipatory request-generator is preferably arranged to generate requests based upon control data and synchronization signals provided by a controller designed for configuring and/or controlling the time-slotted resource-access scheme. The control data includes at least data indicating the relationship between time slots and agents requiring access to the common resource. A single integrated circuit (IC) may comprise a core consisting of a set of modules provided with a core controller of this type.
In some cases, certain of the access-requirements of the agent(s) designed for a time-slotted access scheme may be unpredictable. In other words, the nature of the required access (typically, in terms of the address to be read) may become known only a very short time before the time slot at which the agent is programmed to request access. In such a case, it is advantageous to program the anticipatory request-generator to generate anticipated requests for substantially all of the predictable access-requests, and to adapt the arbitration scheme such that it prioritizes the unpredictable access-requests.
The present invention is of particular interest when applied to systems in which processing modules require access to a common memory. In this case, the controller associated with modules adapted for a time-slotted memory-access scheme will often be adapted to provide address data relative to the read/write operations of each module. The anticipatory request-generator can make use of address data received from the controller in order to generate the anticipated requests. In other cases, the processing modules themselves may generate the address data. In such cases, the anticipatory request-generator collects the necessary address data from the processing modules, when the address data is generated sufficiently early (predictable requests). In general, the core controller or processing modules generate data relating to logical, rather than physical, addresses of an external memory. An associated unit translating between logical and physical addresses is then associated with the core controller/modules.
In systems and methods according to the present invention, in order to ensure that the access-requirements of all agents are properly met, it is preferable to adopt an arbitration scheme in which access-requests of different agents have different priorities. Preferably, this is achieved by using a hierarchical arbitration scheme comprising a plurality of levels, in which time-constrained and periodical access-requests are assigned to a level high up in the hierarchy. Such a hierarchical scheme can be implemented using a cascaded set of state machines, the output from a state machine lower down in the hierarchy serving as an input to a state machine at the next highest level of the hierarchy. At each level in the hierarchy, access-requests compete and the winning request serves as the output from the state machine. The output from the state machine highest in the hierarchy corresponds to the access-request of the agent that has been successful in the arbitration. This access-request will thus be processed (or be placed in a queue of successful requests awaiting processing). This arbitration scheme can be modelled on the hierarchical arbitration scheme described in WO98/12645.
In embodiments of the present invention where the arbiter implements a hierarchical scheme using state machines, it is preferred that for the majority of states of the state machines, fixed priorities are assigned to the different access-requests. However, it is advantageous to ensure that a state machine corresponding to a high level in the hierarchy has free states in which there is no pre-assigned priority between the requests competing at that level.